1. Field of the Invention
The present invention relates generally to semiconductor device design, and more particularly, to a circuit and method for testing an embedded dynamic random access memory (eDRAM) circuit through a test controller with Direct Access mode (DA mode) logic.
2. Description of the Related Art
To reach a fast product ramp up and a high yield, any standard DRAM or embedded DRAM circuit needs intensive testing. Each DRAM contains redundant wordlines and bitlines to enable reparability of defective memory cells. Most of the commonly used DRAM tests are used to find all possible storage cell failures and then collect all these failures in a so-called fail bit map. With this fail bit map, an external tester calculates the best usage of the on-chip redundancy.
DRAMs embedded into ASICs (Application Specific Integrated Circuits) require different test strategies than standalone commodity DRAMs. Embedded DRAMs (eDRAM) often contain a test controller and/or a BIST (Built-In Self-Test) circuit to simplify the testing. Commodity DRAM's normally do not contain any additional test circuits and are tested through a memory tester, whereas eDRAM's are tested together with the other ASIC circuit parts through a logic tester.
FIG. 6 illustrates an example of a typical implementation of a test system for testing an ASIC (Application Specific Integrated Circuit) 601 containing an embedded DRAM 603 (eDRAM). The eDRAM is testable through an on-chip test controller 602 with BIST functionality. The BIST logic circuitry contains test programs and redundancy algorithms to decide if the eDRAM 603 passed or failed the test, i.e., whether the eDRAM is good or bad. An external logic tester 600 could operate this test controller 602 by serially scanning information in (via scan in data line 606), and out (via scan out data line 608) of the chip. Subsequently, the test controller 602 will issue a pass/fail signal via line 610.
However, the test controller with BIST functionality has one major drawback. There is no possibility to collect a fail bit map and to build in complex redundancy calculation methods for enhanced repairability of the ASIC. Low volume products (e.g., ASICs) with a small amount of eDRAM may be acceptable with reduced testability and/or a lower yield. But on high volume products with a larger amount of eDRAM, a high yielding eDRAM is a major contribution to a cost efficient product.
Accordingly, it would be desirable and highly advantageous to have a circuit and method for testing embedded DRAMs on an ASIC which employs a conventional memory tester and has the capability to collect a fail bit map to enable repairability.